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MPT612 maximum power point tracking ic rev. 01 ? 15 june 2010 objective data sheet 1. general description the MPT612, the first dedicated ic for performing the maximum power point tracking (mppt) function, is designed for use in applicat ions that use solar photovoltaic (pv) cells or in fuel cells. to simplify development and maximize system efficiency, the MPT612 is supported by a patent-pending mppt algorithm , an application-specific software library and easy-to-use application programming interfaces (apis). dedicated hardware functions for pv panels, including voltage and current measurement and panel parameter configuration, simplify design and speed development. the MPT612 is based on a low-power arm7td mi-s risc processor that operates at up to 70 mhz and can achieve system efficiency ra tings up to 98 %. it controls the external switching device through a signal derived from a patent-pending mppt algorithm. the dc source can be connected to the ic throu gh appropriate voltage and current sensors. the ic dynamically extracts the maximum power from the dc source, without user intervention. the ic can be configured for boundary conditions set in software. there are up to 15 kb of flash memory available for application software. in this datasheet, solar pv terminology has been primarily used as an example. however, the MPT612 is equally useful for f uel cells or any other dc source which has mpp behavior.
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 2 of 37 2. features and benefits ? arm7tdmi-s 32 bit risc core operating at up to 70 mhz ? 128-bit wide interface and accelera tor enabling 70 mhz operation ? 10-bit adc providing ? eight analog inputs ? conversion times as low as 2.44 s per channel and dedicated result registers minimize interrupt overhead ? five analog inputs available for user specific applications ? one 32-bit timer and external event count er with four capture and four compare channels ? one 16-bit timer and external event counter with three compare channels ? low power real-time clock (rtc) with independent power supply and dedicated 32 khz clock input ? serial interfaces including: ? two uarts (16c550) ? two fast i 2 c-buses (400 kbit/s) ? spi and ssp with buffering and variable data length capabilities ? vectored interrupt controller with conf igurable priorities and vector addresses ? up to twenty eight (28), 5 v tolerant fast general purpose i/o pins ? up to 13 edge or level sensitive external interrupt pins available ? three levels of flash code read protection (crp) ? 70 mhz maximum clock available from programmable on-chip pll with input frequencies between 10 mhz and 25 mhz and a settling time of 100 ms ? integrated oscillator operates with an external crystal at between 1 mhz and 25 mhz ? power saving modes include: ? idle mode ? two power-down modes; one with the rtc active and with the rtc deactivated ? individual enabling/disabling of peripheral functions and peripheral clock scaling for additional power optimization ? processor wake-up from power-down and deep power-down mode using an external interrupt or the rtc 3. applications ? dc application charge controller for solar pv power and fuel-cells. the use cases are ? battery charging for home appliances such as lighting, dc fans, dc tv,dc motor or any other dc appliance ? battery charging for public lighting and signaling - led street lighting, garden/driveway lighting, railway signali ng, traffic signaling, remote telecom terminals/towers etc ? battery charging for portable devices ? dc-dc converter per panel to provide improved efficiency ? micro inverter per panel removes the need for one large system inverter
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 3 of 37 4. ordering information table 1. ordering information package type number name description version MPT612fbd48 lqfp48 plastic low profile quad flat package; 48 leads; body 7 7 1.4 mm sot313-2 5. block diagram the configuration parameters are determined using the software fig 1. block diagram 001aam089 pv voltage measurement pv voltage sense pv current measurement pv current sense battery voltage measurement battery voltage sense battery current measurement battery current sense temperature measurement temperature sense load current measurement these blocks are needed for mppt functionality these blocks can be used for customer specific application pv configuration block MPT612 mppt alogirthm battery charge cycle algorithm battery configuration block load management load configuration block load configuration parameters battery configuration parameters status indication pv configuration parameters switch circuit control battery protection block load protection leds pwm battery load load current sense
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 4 of 37 6. pinning information 6.1 pinning fig 2. pin configuration MPT612fbd48 pio19/mat1_2/miso1 pio11/cts1/cap1_1/ad4 pio20/mat1_3/mosi1 pio10/rts1/cap1_0/ad3 pio21/ssel1/mat3_0 pvcurrentsense v dd(rtc) pvvoltsenseboost v ddc pvvoltsensebuck rst gndadc gnd pio9/rxd1/pwmout2 pio27/trst pio8/txd1/pwmout1 pio28/tms pwmout0 pio29/tck jtagsel xtal1 rtck xtal2 rtcx2 pio18/cap1_3/sda1 pio17/cap1_2/scl1 pio16/eint0 pio15/ri1/eint2 pio14/dcd1/sck1/eint1 gnd v dd(adc) pio13/dtr1/mat1_1 v dd(io) pio26/ad7 pio25/ad6 pio12/dsr1/mat1_0/ad5 pio0/txd0/mat3_1 pio1/rxd0/mat3_2 pio30/tdi/mat3_3 pio31/tdo v dd(io) pio2/scl0 gnd rtcx1 pio3/sda0 pio4/sck0 pio5/miso0 pio6/mosi0 001aam091 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 48 47 46 45 44 43 42 41 40 39 38 37 24
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 5 of 37 6.2 pin description table 2. pin description symbol pin type description pio0 to pio30 i/o pio0 to pio30: 31 pins for general purpose bidirectional digital input and output (gpio). the operat ion of these pins is dependent on the selected pin function. the functions of pins pio7, pio22, pio23 and pio24 are not defined as in the gpio; do not change these settings. pio31 16 o pio31 is a digital output pin. i/o pio0: general purpose digital input and output pin o txd0: transmitter output for uart0 pio0/txd0/mat3_1 13 [1] o mat3_1: pwm output 1 for timer 3 i/o pio1: general purpose digital input and output pin i rxd0: receiver input for uart0 pio1/rxd0/mat3_2 14 [1] o mat3_2: pwm output 2 for timer 3 i/o pio2: general purpose digital input and output pin; open-drain output pio2/scl0 18 [2] i/o scl0: i 2 c-bus port 0 clock input and output; open-drain output i/o pio3: general purpose digital input and output pin; open-drain output pio3/sda0 21 [2] i/o sda0: i 2 c-bus port 0 data input and output; open-drain output i/o pio4: general purpose digital input and output pin. pio4/sck0 22 [1] i/o sck0: serial clock for spi0; spi clock output from master or input to slave. i/o pio5: general purpose digital input and output pin pio5/miso0 23 [1] i/o miso0: master in slave out for spi0; data input to spi master or data output from spi slave i/o pio6: general purpose digital input and output pin pio6/mosi0 24 [1] i/o mosi0: master out slave in for spi0; dat a output from spi master or data input to spi slave pwmout0 28 [1] o pwmout0: pwm output used for switchin g the device; do not use for anything else i/o pio8: general purpose digital input and output pin o txd1: transmitter output for uart1 pio8/txd1/pwmout1 29 [1] o pwmout1: pwm output; same frequency as pwmout0, however, the duty cycle can be changed i/o pio9: general purpose digital input and output pin i rxd1: receiver input for uart1 pio9/rxd1/pwmout2 30 [1] o pwmout2: pwm output; same frequency as pwmout0, however, the duty cycle can be changed i/o pio10: general purpose digital input and output pin o rts1: request to send output for uart1 i cap1_0: capture input for timer 1, channel 0 pio10/rts1/cap1_0/ad3 35 [3] i ad3: analog-to-digital converter input 3
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 6 of 37 symbol pin type description i/o pio11: general purpose digital input and output pin i cts1: clear to send input for uart1 i cap1_1: capture input for timer 1, channel 1 pio11/cts1/cap1_1/ad4 36 [3] i ad4: analog-to-digital converter input 4 i/o pio12: general purpose digital input and output pin i dsr1: data set ready input for uart1 o mat1_0: pwm output for timer 1, channel 0 pio12/dsr1/mat1_0/ad5 37 [3] i ad5: analog-to-digital converter input 5 i/o pio13: general purpose digital input and output pin o dtr1: data terminal ready output for uart1 pio13/dtr1/mat1_1 41 [1] o mat1_1: pwm output for timer 1, channel 1 i/o pio14: general purpose digital input and output pin i dcd1: data carrier detect input for uart1 i/o sck1: serial clock for spi1; spi clock out put from master or input to slave pio14/dcd1/sck1/eint1 44 [4] [5] i eint1: external interrupt input 1 i/o pio15: general purpose digital input and output pin i ri1: ring indicator input for uart1 pio15/ri1/eint2 45 [4] i eint2: external interrupt input 2 i/o pio16: general purpose digital input and output pin pio16/eint0 46 [4] i eint0: external interrupt input 0 i/o pio17: general purpose digital input and output pin; the output is not open- drain i cap1_2: capture input for timer 1, channel 2 pio17/cap1_2/scl1 47 [6] i/o scl1: i 2 c-bus port 1 clock input and output; open-drain output if i 2 c1 function is selected on the pin connect block i/o pio18: general purpose digital input and output pin; the output is not open- drain i cap1_3: capture input for timer 1, channel 3 pio18/cap1_3/sda1 48 [6] i/o sda1: i 2 c-bus port 1 data input and out put; open-drain output if i 2 c1 function is selected on the pin connect block i/o pio19: general purpose digital input and output pin. o mat1_2: pwm output for timer 1, channel 2 pio19/mat1_2/miso1 1 [1] i/o miso1: master in slave out for ssp; data input to ssp master or data output from ssp slave. i/o pio20: general purpose digital input and output pin o mat1_3: pwm output for timer 1, channel 3 pio20/mat1_3/mosi1 2 [1] i/o mosi1: master out slave for ssp; data output from ssp master or data input to ssp slave i/o pio21: general purpose digital input and output pin i ssel1: slave select for spi1; select s the spi interface as a slave pio21/ssel1/mat3_0 3 [1] o mat3_0: pwm output for timer 3, channel 0 pvvoltsensebuck 32 [3] i pv voltage sense for buck mode
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 7 of 37 symbol pin type description pvvoltsenseboost 33 [3] i pv voltage sense for boost mode; this pin is not connected when only buck mode is used pvcurrentsense 34 [3] i pv current sense. i/o pio25: general purpose digital input and output pin. pio25/ad6 38 [3] i ad6: analog-to-digital converter input 6 i/o pio26: general purpose digital input and output pin pio26/ad7 39 [3] i ad7: analog-to-digital input 7 i/o pio27: general purpose digital input and output pin pio27/ trst 8 [1] i trst : test reset for the jtag interface [6] i/o pio28: general purpose digital input and output pin. pio28/tms 9 [1] i tms: test mode select for the jtag interface [6] i/o pio29: general purpose input/output digital pin. pio29/tck 10 [1] i tck: test clock for the jtag interface [6] this clock must be slower than 1 / 6 of the cpu clock (cclk) for the jtag interface to operate i/o pio30: general purpose digital input and output pin i tdi: test data in for jtag interface [6] pio30/tdi/mat3_3 15 [1] o mat3_3: pwm output 3 for timer 3 o pio31: general purpose digital output pin pio31/tdo 16 [1] o tdo: test data out for jtag interface [6] rtcx1 20 [8] [9] i rtc oscillator circuit input; the in put voltage must not exceed 1.8 v rtcx2 25 [8] [9] o rtc oscillator circuit output rtck 26 [8] i/o returned test clock output; bidirectional pin with inte rnal pull-up; extra signal added to the jtag port. assists debugger synchronization when processor frequency varies xtal1 11 i oscillator and internal clock g enerator circuit input; the input voltage must not exceed 1.8 v xtal2 12 o oscillator amplifier output jtagsel 27 i jtag interface select; input with internal pull-down: when low, the device operates normally when externally pulled high at reset, pio27 to pio31 are configured as jtag port and the part is in debug mode rst 6 i external reset input; ttl with hysteresis; 5 v tolerant when low, this pin resets the devic e; all i/o ports and peripherals return to their default states and processor execution will begin at address 0x00 gnd 7,19,4 3 i ground; 0 v reference gndadc 31 i analog ground 0 v reference; nom inally the same voltage as gnd but should be isolated to minimize noise and error v dd(adc) 42 i analog 3.3 v power supply; nominally the same voltage as v dd(io) but should be isolated to minimize noise and error; the level on this pin provides the adc voltage reference level v ddc 5 i 1.8 v core power supply; internal circuitry and on-chip pll power supply voltage
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 8 of 37 symbol pin type description v dd(io) 17,40 i 3.3 v pad power supply; i/o ports power supply voltage v dd(rtc) 4 i 3.3 v rtc power supply. on this pin supplies the power to the rtc. [1] 5 v tolerant (if v dd(io) and v dd(adc) 3.0 v) pad providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. [2] open-drain, 5 v tolerant (if v dd(io) and v dd(adc) 3.0 v) digital i/o i 2 c-bus 400 khz specification compatible pad. it requires external pull-up to provide output functionality. open-drain c onfiguration applies to all functions on that pin. [3] 5 v tolerant (if v dd(io) and v dd(adc) 3.0 v) pad providing digital i/o (with ttl levels and hysteresis and 10 ns slew rate control) and analog input function. if configured for an i nput function, this pad utilizes built-in g litch filter that blocks pulses shorter than 3 ns. when configured as an adc input, digital section of the pad is disabled. [4] 5 v tolerant (if v dd(io) and v dd(adc) 3.0 v) pad providing digital i/o functions with ttl levels and hysteresis and 10 ns slew rate control. if configured for an input function, this pad utilizes built-in glitch filter that blocks pulses shorter than 3 ns. [5] a low level during reset on pin pio14 is considered as an external hardware request to start the isp command handler. [6] when pin jtagsel is high, this pin is automatically configured for use with embeddedice in debug mode. [7] open-drain, 5 v tolerant (if v dd(io) and v dd(adc) 3.0 v) digital i/o i 2 c-bus 400 khz specification compatible pad. it requires external pull-up to provide output functionality. op en-drain configuration applies only to i 2 c-bus function on that pin. [8] pad provides spec ial analog functionality. [9] pin should be left floating when the rtc is not used for the lowest power consumption.
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 9 of 37 7. functional description 7.1 architectural overview the arm7tdmi-s is a general purpose 32-bit processor core offering high performance and very low power consumption. the arm arch itecture is based on reduced instruction set computer (risc) principles making the instruction set and decode mechanisms are much simpler than those of micro programmed complex instruction set computers (cisc). this simplicity results in a high in struction throughput and impressive real-time interrupt response from a small, cost-effective processor core. pipeline techniques are employed ensuring a ll parts of the processing and memory systems can operate continuously. typically, while one instru ction is being executed, its successor is being decoded and a third in struction is being read from memory. the arm7tdmi-s processor also employs a unique architectural strategy known as thumb which makes it ideally suited to high-volume applications with memory restrictions, or applications w here code density is an issue. the key idea behind thumb is a super-r educed instruction set. essentially, the arm7tdmi-s processor has two instruction sets: ? the standard 32-bit arm set ? the 16-bit thumb set the thumb set?s 16-bit instruction length allows it to approach twice the density of standard arm code while retaining most of the arm?s performance advantage over a traditional 16-bit processor using 16-bit regist ers. this is possible because thumb code operates on the same 32-bit register set as arm code. thumb code provides up to 65 % of the code size of arm and 160 % of the performance of an equivalent arm processor connected to a 16-bit memory system. the particular flash implementation in the MPT612 also allows full speed execution in arm mode. it is recommended to program perfo rmance critical and short code sections in arm mode. the impact on the overall code size is minimal but the speed can be increased by 30 % over thumb mode. 7.2 on-chip flash program memory the MPT612 incorporates a 32 kb flash memo ry system. this memory can be used for both code and data storage. programming flash memory can be performed in several ways. it can be programmed in system using the serial port. the application program can also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field firmwa re upgrades, etc. the entire flash memory is available for user code as the boot loader resides in a separate memory. the MPT612 flash memory provides a mi nimum of 100 000 erase/write cycles and 20 years of data-retention memory. 7.3 on-chip static ram on-chip static ram may be used for code and/or data storage. the sram may be accessed as 8-bit, 16-bit and 32-bit. the mp t612 provide 8 kb of static ram.
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 10 of 37 7.4 memory map the MPT612 memory map incorporates several distinct regions, as shown in fig 3 . in addition, the cpu interrupt vect ors can be re-mapped to allow them to reside in either flash memory (the default) or on-chip static ram. 001aam090 ahb peripherals 0xffff ffff 0xf000 0000 0xe000 0000 4.0 gb 3.75 gb 3.5 gb 0xc000 0000 0x4000 0000 0x8000 0000 0x7fff e000 0x7fff dfff 0x4000 2000 0x4000 1fff 0x0000 8000 0x0000 0000 0.0 gb 1.0 gb 2.0 gb 3.0 gb 0x0000 7fff apb peripherals reserved address space boot block reserved address space reserved address space 8 kb on-chip static ram 32 kb on-chip non-volatile memory fig 3. system memory map 7.5 interrupt controller the vic accepts all of the inte rrupt request inputs and categorizes them as fiq, vectored irq and non-vectored irq as defined by programmable settings. the programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. fiq has the highest priority. if more than one request is assigned to fiq, the vic combines the requests to produce the fiq signal to the arm processor. the fastest possible fiq latency is achieved when only one request is classified as fiq because the fiq service routine does not need to branch into the interrupt service routine but can run
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 11 of 37 from the interrupt vector location. if more than one request is assigned to the fiq class, the fiq service routine reads a word from t he vic that identifies which fiq sources are requesting an interrupt. vectored irqs have the middle priority. sixteen of the interrupt requests can be assigned to this category. any of the interrupt req uests can be assigned to any of the 16 vectored irq slots. slot 0 has the highest priori ty and slot 15 has the lowest priority. non-vectored irqs have the lowest priority. the vic combines the requests from all the vectored and non-vectored irqs to generate the irq signal for the arm processor. the irq service routine can start by reading a register from the vic and jumping to it. if any vectored irqs are pending, the vic provides the address of the highe st priority requesting irqs se rvice routine, otherwise it provides the address of a default routine whic h is shared by all the non-vectored irqs. the default routine can read another vic regi ster to see which irqs are active. 7.5.1 interrupt sources each peripheral device has one interrupt li ne connected to the vic which can contain several internal interrupt flags. each indivi dual interrupt flag can represent more than one interrupt source. 7.6 pin connect block the pin connect block enables selected device pins to have more than one function. configuration registers control the multiple xers to allow connection between the pin and the on chip peripherals. peripherals should be connected to the appropriate pins before being activated and any related interrupt(s) are enabled. activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. the pin control module with its pin select registers defines the functionality of the processor core in a given hardware environment. after reset, all pins of pio are configured as inputs with the following exception: ? if the jtagsel pin is high (debug mode ena bled), the jtag pins will assume their jtag functionality for use with embeddedice and cannot be configured via the pin connect block. 7.7 fast general purpose parallel i/o pins that are not connected to a specific peripheral function are controlled by the gpio registers. pins can be dynami cally configured as inputs or outputs. separate registers allow simultaneous setting or clearing any number of outputs. the value of the output register and the state of the port pins can be read back. the gpio provides the following features: ? gpio registers are relocated for the fastest possible i/o timing ? mask registers allow sets of port bits to be treated as a group, leaving other bits unchanged ? all gpio registers are byte addressable ? entire port value can be written in one instruction ? bit level set and clear registers allow a single instruction setting or clearing of any number of bits on one port ? direction control of individual bits
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 12 of 37 ? separate control of output set and clear ? all i/o default to inputs after reset 7.8 10-bit adc the MPT612 contains one analog-to-digita l converter (adc). it is a single 10-bit successive approximation adc with eight c hannels, three of which are used internally. the adc provides the following features: ? measurement range from 0 v to 3.3 v ? the converter can perform more than 400 000 10-bit samples per second ? burst conversion mode for single or multiple inputs ? optional conversion on input pin transition or timer match signal ? every analog input has a dedicated result register to reduce interrupt overhead 7.9 uarts the MPT612 contain two uarts. in addition to standard transmit and receive data lines uart1 also provides a full modem control handshake interface. the uarts in MPT612 include a fractional baud rate generator fo r both uarts. standard baud rates such as 115200 can be achieved with any crystal fr equency above 2 mhz. the uarts provide the following features: ? 16-byte receive and transmit fifos ? register locations conform to 16c550 industry standard ? receiver fifo trigger points at 1-byte, 4-byte, 8-byte and 14-byte ? built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals ? transmission fifo control enables implementation of software flow control (xon/xoff) on both uarts ? uart1 is equipped with standard modem interface signals. this module also provides full support for hardwar e flow control (auto-cts/rts) 7.10 i 2 c-bus serial i/o controllers the MPT612 contains two i 2 c-bus controllers. the i 2 c-bus is bidirectional, 2-wire interface providing the serial clock line (scl) and the serial data line (sda). each i 2 c-bus device is recognized by a unique address and can operate as either a receiver-only device (e.g., lcd driver) or a transmitter with the capability to both receive and send information such as se rial memory. transmitters and/or receivers can operate in either mast er or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c-bus is a multi-master bus; it can be controlled by more than one bus master connected to it. the i 2 c-bus implemented in the MPT612 supports bit rates up to 400 kbit/s (fast i 2 c-bus). the controller provides the following features: ? compliant with standard i 2 c-bus interface specification ? easy to configure as master, slave or master/slave ? programmable clocks allow versatile rate control ? bidirectional data transfer between masters and slaves
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 13 of 37 ? multi-master bus (no central master) ? arbitration between simultaneously transmi tting masters without corruption of serial data on the bus ? serial clock synchronization allows devices with different bit rates to communicate using one serial bus ? serial clock synchronization can be us ed as a handshake mechanism to suspend and resume serial transfer ? the i 2 c-bus can also be used for test and diagnostic purposes 7.11 spi serial i/o controller the MPT612 contains one spi i/o controlle r. spi is a full duplex serial peripheral interface, designed to handle multiple master s and slaves connected to a given bus. only a single master and a single slave can communi cate on the interface during a given data transfer. during a data transfer the master and slave always send 8 bits to 16 bits of data to each other. the controller provides the following features: ? compliant with spi specification ? synchronous, serial, full duplex, communication ? spi master only ? maximum data bit rate of one eighth of the input clock rate 7.12 ssp serial i/o controller the MPT612 contains one ssp. the ssp cont roller is capable of operation on using spi, a 4-wire ssi or microwire bus. it can in teract with multiple masters and slaves on the bus. however, only a single master and a single slave can communicate on the bus during a given data transfer. t he ssp supports full duplex transf ers, with data frames of 4 bits to 16 bits flowing from the master to the slave and from the slave to the master. often only one of these data streams carries meaningful data. the controller provides the following features: ? compatible with motorola spi, texas instruments 4-wire ssi and national semiconductor?s microwire buses ? synchronous serial communication ? master or slave operation ? 8-frame fifos for both transmit and receive ? four bits to 16 bits per frame 7.13 general purpose 32-bit timers/external event counters the timer/counter is designed to count cycles of: ? the peripheral clock (pclk) ? an externally supplied clock and optionally generate interrupts ? perform other actions at specified timer values, based on four match registers. it includes four capture inputs to trap the timer value when input signals transition which can optionally generate an interrupt. multiple pins can be selected to perform a single capture or match function, for example to provide an application with logica l or, and and ?broadcast? functions.
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 14 of 37 the MPT612 can count external events on one of the capture inputs, if the minimum external pulse width is equal to or longer t han a period of pclk. in this configuration, unused capture lines can be selected as regular timer capture inputs or used as external interrupts. the event counter pr ovides the following features: ? a 32-bit timer/counter with a programmable 32-bit prescaler ? external event counter or timer operation ? four 32-bit capture channels per timer/co unter that can take timer value snapshot when an input signal transitions. a capture event can optionally generate an interrupt ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match ? stop timer on match with optional interrupt generation ? reset timer on match with optional interrupt generation ? four external outputs per timer/counter corresponding to match registers with the following capabilities: ? set low on match ? set high on match ? toggle on match ? do nothing on match 7.14 general purpose 16-bit timers/external event counters the timer/counter is designed to count cycl es of the peripheral clock (pclk) or an externally supplied clock. optionally inte rrupts can be generated or other actions performed at specified timer values, based on the contents of four match registers. in addition, three capture inputs can be used to trap the timer value when input signals transition and optionally to generate an interrupt. multiple pins can be selected to perform a single capture or match function, provid ing an application with logical or, and and ?broadcast? functions. the MPT612 can count external events on one of the capture inputs when the minimum external pulse is equal to or longer than a pclk period. in this configuration, unused capture lines can be selected as regular ti mer capture inputs or used as external interrupts. the timer/counter provides the following features: ? one 16-bit timer/counter with a programmable 16-bit prescaler ? external event counter or timer operation ? four 16-bit match registers that allow: ? continuous operation with optional interrupt generation on match ? stop timer on match with optional interrupt generation ? reset timer on match with optional interrupt generation ? four external outputs per timer/counter co rresponding to match registers, with the following capabilities: ? set low on match ? set high on match ? toggle on match ? do nothing on match
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 15 of 37 7.15 watchdog timer the purpose of the watchdog timer is to reset the processor core after a given time if it enters an error state. when enabl ed, the watchdog generates a system reset if the user program fails to reload the watchdog within the predetermined time. the watchdog timer provides the following features: ? internal device reset if not periodically reloaded ? debug mode ? enabled by software but requires a hardware reset or watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence causes reset/interrupt, if enabled ? flag to indicate watchdog reset ? programmable 32-bit timer with internal prescaler ? selectable time period from (t pclk 256 4) to (t pclk 232 4) in multiples of t pclk 4. 7.16 real-time clock the real-time clock (rtc) is designed to provide a set of counters to measure time when normal or idle operating mode is selected. the rtc has been designed to use minimal power, making it suitable for batte ry powered systems w here the cpu is not running continuously (idle mode). the rtc provides the following features: ? measures the passage of time to maintain a calendar and clock ? ultra-low power design to support battery powered systems ? provides seconds, minutes, hours, day of the month, month, year, day of the week and day of the year ? uses either the dedicated internal 32 kh z rtc oscillator input or the clock derived from the external crystal/o scillator input on pin xtal1 ? the programmable reference clock divider allows fine adjustment of the rtc ? dedicated power supply pin can be connected to a battery or the main 3.3 v supply 7.17 system control 7.17.1 crystal oscillator the on-chip integrated oscillator operates wi th external crystal in range of 1 mhz to 25 mhz. the oscillator output frequency is f osc and the arm processor clock frequency is cclk. f osc and cclk are the same value unless the pll is running and connected. 7.17.2 pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up into the range of 10 mhz to 70 mhz by a current controlled oscillator (cco). the multiplier can be an integer value from 1 to 32. in practice however, the multiplier value cannot be higher than 6 on this family of processor cores due to the cpus upper frequency limit. the cco operates in a range from 156 mhz to 320 mhz, this forms an additional divider in the loop to keep the cco within its fr equency range while the pll is providing the required output frequency.
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 16 of 37 the output divider can be set to divide by a fact or of 2, 4, 8 or 16 to produce the output clock. the minimum output divider value is 2 which gives a pll output with a 50 % duty cycle. the pll is turned off and bypassed after a device reset and can be enabled using the software. the program must configure and ac tivate the pll, wait for the pll to lock and then connect to the pll as a clock source. the pll settling time is 100 s. 7.17.3 reset and wake-up timer the MPT612 reset has two sources; one from the rst pin and the other from the watchdog reset. the rst pin is a schmitt trigger input pin with an additional glitch filter. assertion of device reset by any source starts the wake-up timer (see section 7.17.3.1 ). this causes the internal device reset to remain asserted until: ? the external reset is deasserted ? the oscillator is running ? a fixed number of clocks have passed ? the on-chip flash controller has completed its initialization when the internal reset is removed, all of the processor core and peripheral registers are been re-initialized to their reset values and the core begins executing from the reset vector (address 0). 7.17.3.1 wake-up timer description the wake-up timer ensures that the oscill ator and other analog functions required for device operation are fully functional befor e the processor is allowed to execute instructions. this is important during power on , all types of reset and whenever any of the functions are turned off. since the oscillat or and other functions are turned off during power-down and in deep power-down mode, a wa ke-up of the core from these modes makes use of the wake-up timer. the wake-up timer monitors the crystal oscillato r to check when it is safe to begin code execution. a stabilization time interval is r equired for the oscillator to produce a signal of sufficient amplitude to drive the clock logic when power is applied to the device or an event causes the chip to exit power-down mode. the amount of time depends on many factors, including: ? the rate of v dd ramp up (in the case of power on), ? the type of crystal, its electrical characterist ics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), ? the characteristics of the oscillato r under the existing ambient conditions
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 17 of 37 7.17.4 code security (code read protection) the MPT612?s code read protection (crp) featur e allows users to restrict access to the on-board flash, jtag and isp using different levels of security. when needed, crp is activated by programming a specific pattern into a dedicated flash location. iap commands are not affected by the crp. three levels of the crp are implemented in boot loader code: ? crp1: disables access to chip via the jtag pins and allows partial flash updates (excluding flash sector 0) using a limited set of the isp commands. this mode is useful when crp is required and flash field updates are needed but all sectors cannot be erased ? crp2: disables access to chip via the jtag pins and only allows full flash erase and update using a reduced set of the isp commands ? crp3: running an application with this level fully disables any access to chip via the jtag pins and the isp. this mode effectiv ely disables isp override using pio14 pin. it is up to the user?s application to provide a flash update mechanism (if needed) using iap calls or call the re-invoke isp command to enable flash update via pin uart0. caution if code read protection level three (crp3) is selected, no future factory testing can be performed on the device. 7.17.5 external interrupt inputs the MPT612 includes up to three edge or level sensitive external interrupt inputs as selectable pin functions. when the pins are combined, external events can be processed as three independent interrupt signals. opti onally, the external interrupt inputs can be used to wake-up the processor from power-down mode and deep power-down mode. in additional, all 10 capture input pins can also be used as external interrupts without the option to wake the device up from power-down mode. 7.17.6 memory mapping control the memory mapping control changes the m apping of the interrupt vectors that appear beginning at address 0x0000 0000. vectors c an be mapped to the bottom of the on-chip flash memory or to the on-chip static ram. this allows code running in different memory spaces to have control of the interrupts. 7.17.7 power control the MPT612 supports three reduced power modes: idle mode, power-down mode and deep power-down mode. in idle mode, execution of instructions is su spended until a reset or interrupt is received. peripheral functions continue operation in idle mode and can generate interrupts which cause the processor to resume execution. idle mode eliminates power used by the processor itself, memory systems and related controllers and internal buses. in power-down mode, the oscillator is shut down and the chip receives no internal clock signals. the processor state and registers, peripheral registers and internal sram
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 18 of 37 values are preserved throughout power-down mode. in addition, the logic levels of chip output pins remain static. power-down mode can be exited and normal operation resumed by either a reset or via specific in terrupts that function wi thout clock signals. power-down mode reduces chip power consumpt ion to nearly zero because all dynamic device operation is suspended. selecting an external 32 khz clock instead of the pclk as the clock-source for the on-chip rtc enables the core to keep the rtc active during power-down mode. power- down current is increased when the rtc is ac tive. however, the current consumption is significantly lower than that in idle mode. in deep-power down mode, all power is remov ed from the internal chip logic except for the rtc module, the i/o ports, the sram and the 32 khz external oscillator. additional power savings are provided when sram and the 32 khz oscillator are powered down individually. deep power-down mode has the lo west possible power consumption without removing power from the entire chip. in deep power-down mode, the contents of registers and memory are not preserved exc ept for sram (if selected) and three general purpose registers. to resume operation, a full chip reset is required. to conserve battery power, a power selector module switches the rtc power supply from v dd(rtc) to v ddc whenever the core voltage is present on pin v ddc . a power control feature for peripherals enables individual peripherals to be turned off when they are not needed in the application. this results in additional power savings during active and idle modes. 7.17.8 apb the apb divider determines the relationship between the processor clock (cclk) and the clock used for peripheral devices (pclk) . the apb divider serves two purposes. the first is to provide peripherals with the desi red pclk via the apb divider so that they can operate at the chosen arm processor speed. in order to achieve this, the apb divider may be slowed down to between 50 % and 25 % of the processor clock rate. the default condition on reset is the apb divider running at 25 % of the processor clock rate. this is because the apb divider must work correctly dur ing power-up (and its timing cannot be altered if it does not work since its c ontrol registers reside on the apb). the second purpose of the apb divider is to allow powe r saving when an applicat ion does not require any peripherals running at the full processor rate. the pll remains active (if it was running) during idle mode because the apb divider is connected to the pll output. 7.17.9 emulation and debugging the MPT612 supports emulation and debugging using the jtag serial port. 7.17.10 embeddedice standard arm embeddedice logic provides on-chip debug support. debugging of the target system requires a host comput er running the debugger software and an embeddedice protocol converter. the embedd edice protocol converter converts the remote debug protocol commands to the jtag data needed for accessing the arm core. the arm core contains a built-in a debug communication channel function. the debug communication channel allows a program running on the target system to communicate with the host debugger/another host without stopping the program flow or entering the debug state. the debug communication channel is accessed as coprocessor 14 by the program running on the arm7tdmi-s core. the debug communication channel allows the jtag
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 19 of 37 port to be used for sending and receiving data without affecting the normal program flow. the debug communication channel data and control registers are mapped in to addresses in the embeddedice logic. the jtag clock (tck) must be slower than 1 / 6 of the cpu clock (cclk) to enable the jtag interface to operate. 7.17.11 realmonitor realmonitor is a configurable software module, developed by arm inc. which enables real time debugging. it is a lightweight debug monitor that runs in the background while users debug the foreground application. it communicates with the host using dcc which is present in the embeddedice logic. the MPT612 contain a specific configuration of realmonitor software programmed into the on-chip boot rom memory. 8. limiting values table 3. limiting values in accordance wi th the absolute maximum rating system (iec 60134). [1] symbol parameter conditions min max unit v ddc core supply voltage typical: 1.8 v [1]b) ? 0.5 +2.5 v v dd(io) input/output supply volt age typical: 3.3 v [2] ? 0.5 +4.6 v v dd(adc) adc supply voltage pad supply: 3.3 v ? 0.5 +4.6 v v dd(rtc) rtc supply voltage ? 0.5 +4.6 v v ia analog input voltage [3] ? 0.5 +5.1 v 5 v tolerant i/o pins [4] [5] ? 0.5 +6.0 v v i input voltage other i/o pins [4] [5] ? 0.5 v dd(io) + 0.5 [6] v i dd supply current [7] - 100 [8] ma i ss ground current [9] - 100 [8] ma t stg storage temperature [10] ? 65 +150 c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption - 1.5 w human body model (hbm) [ [11] ? 4000 +4000 v machine model (mm) [12] ? 200 +200 v v esd electrostatic discharge voltage charged device model (cdm) [13] ? 800 +800 v [1] the following applies to the limiting values: a) this product includes circuitry specific ally designed for the protection of its in ternal devices from the damaging effects o f excessive static charge. nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. parameters are valid over operating temperature range unl ess otherwise specified. all voltages are with respect to gnd unless otherwise noted. b) core and internal rail [2] external rail [3] on adc related pins [4] including voltage on outputs in 3-state mode [5] only valid when the v dd(io) supply voltage is present [6] not to exceed 4.6 v [7] per supply pin [8] the peak current is limited to 25 times the corresponding maximum current [9] per ground pin [10] dependent on package type
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 20 of 37 [11] performed per aec-q100-002 [12] performed per aec-q100-003 [13] performed per aec-q100-011 9. static characteristics table 4. static characteristics [1] symbol parameter conditions min typ max unit v ddc core supply voltage [2] 1.65 1.8 1.95 v v dd(io) input/output supply voltage [3] 2.6 [4] 3.3 3.6 v v dd(adc) adc supply voltage pad supply 2.6 [5] 3.3 3.6 v v dd(rtc) rtc supply voltage 2.0 [6] 3.3 3.6 v standard port pins, rst , rtck i il low-level input current v i = 0 v; no pull-up - - 3 ma i ih high-level input current v i = v dd(io) ; no pull-down - - 3 ma i oz off-state output current v o = 0 v, v o = v dd(io) ; no pull-up or pull-down - - 3 ma i latch i/o latch-up current ? (0.5v dd(io) ) < v i < (1.5v dd(io) ); t j < 125 c - - 100 ma pin configured to provide a digital function; v dd(io) and v dd(adc) 3 v [7] [8] [9] 0 - 5.5 v v i input voltage pin configured to provide a digital function; v dd(io) and v dd(adc) < 3 v [7] [8] [9] 0 - v dd(io) v v o output voltage output active 0 - v dd(io) v v ih high-level input voltage 2 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage 0.4 - - v v oh high-level output voltage i oh = ? 4 ma v dd(io) ? 0.4 - - v v ol low-level output voltage i ol = ? 4 ma [10] - - 0.4 v i oh high-level output current v oh = v dd(io) ? 0.4 v [10] ? 4 - - ma i ol low-level output current v ol = 0.4 v [10] 4 - - ma i ohs high-level short- circuit output current v oh = 0 v [11] - - ? 45 ma i ols low-level short-circuit output current v ol = v dd(adc) [11] - - 50 ma i pd pull-down current v i = 5 v [12] 10 50 150 ma
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 21 of 37 symbol parameter conditions min typ max unit v i = 0 v [13] ? 15 ? 50 ? 85 ma i pu pull-up current v dd(io) < v i < 5 v [12] 0 0 0 ma active mode; code while (1){} executed from flash; all peripherals enabled via pconp register but not configured to run; cclk = 70 mhz v ddc = 1.8 v; t amb = 25 c - 41 70 ma power-down mode; v ddc = 1.8 v; t amb = 25 c - 2.5 25 ma v ddc = 1.8 v; t amb = 85 c - 35 105 ma deep power-down mode rtc off; sram off; t amb = 25 c i ddc core supply current v dd(rtc) = 3.3 v; v ddc = 1.8 v - 0.7 - ma active mode cclk = 70 mhz; pclk = 12.5 mhz; pclk enabled to rtck; rtc clock = 32 khz (from rtcx pins); t amb = 25 c [14] v ddc = 1.8 v; v dd(rtc) = 3.0 v - 10 15 ma power-down mode rtc clock = 32 khz (from rtcx pins); t amb = 25 c v ddc = 1.8 v; v dd(rtc) = 2.5 v - 7 12 ma v ddc = 1.8 v; v dd(rtc) = 3.0 v - 8 12 ma deep power-down mode rtc off; sram off; t amb = 25 c i dd(rtc) rtc supply current v ddc = 1.8 v; v dd(rtc) = 3.0 v - 8 - ma i 2 c-bus pins v ih high-level input voltage 0.7 v dd(io) - - v v il low-level input voltage - - 0.3 v dd(io) v v hys hysteresis voltage - 0.5 v dd(io) - v v ol low-level output voltage i ols = 3 ma [10] - - 0.4 v i li input leakage current v i = v dd(io) - 2 4 ma v i = 5 v [15] - 10 22 ma
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 22 of 37 symbol parameter conditions min typ max unit oscillator pins v i(xtal1) input voltage on pin xtal1 0 - 1.8 v v o(xtal2) output voltage on pin xtal2 0 - 1.8 v v i(rtcx1) input voltage on pin rtcx1 0 - 1.8 v v o(rtcx2) output voltage on pin rtcx2 0 - 1.8 v [1] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages. [2] core and internal rail. [3] external rail. [4] if v dd(io) < 3.0 v, the i/o pins are not 5 v tolerant and the adc input voltage is limited to v dd(adc) = 3.0 v. [5] if v dd(adc) < 3.0 v, the i/o pins are not 5 v tolerant. [6] the rtc typically fails when v dd(rtc) drops below 1.6 v. [7] including voltage on outputs in 3-state mode. [8] v dd(io) supply voltages must be present. [9] 3-state outputs go into 3-state mode when v dd(io) is grounded. [10] accounts for 100 mv voltage drop in all supply lines. [11] allowed as long as the current limit does not exceed the maximum current allowed by the device. [12] minimum condition for v i = 4.5 v, maximum condition for v i = 5.5 v. v dd(adc) ? ? 3.0 v and v dd(io) ? ??3.0 v. [13] applies to pio25:16. [14] battery supply current on pin v dd(rtc) . [15] input leakage current to gnd. table 5. adc static characteristics v dd(adc) = 2.5 v to 3.6 v; t amb = -40 c to +85 c unless otherwise specified. adc frequency 4.5 mhz symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dd(adc) v c ia analog input capacitance - - 1 pf e d differential linearity error [1] [2] [3] - - 1 lsb e l(adj) integral non-linearity [1] [2] [4] - - 2 lsb e o offset error [1] [5] - - 3 lsb e g gain error [1] [6] - - 0.5 % e t absolute error [1] [7] - - 4 lsb [1] conditions: gndadc = 0 v, v dd(adc) = 3.3 v and v dd(io) = 3.3 v for 10-bit resolution at full speed; v dd(adc) = 2.6 v, v dd(io) = 2.6 v for 8-bit resolution at full speed. [2] the adc is monotonic, there are no missing codes. [3] the differential linearity error (e d ) is the difference between the actual st ep width and the ideal step width. see fig 4. [4] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see fig 4. [5] the offset error (e o ) is the absolute difference between the st raight line which fits the actual curv e and the straight line which fits the ideal curve. see fig 4. [6] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error and the straight line which fi ts the ideal transfer curve. see fig 4. [7] the absolute error (e t ) is the maximum difference between the center of the st eps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see fig 4.
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 23 of 37 002aac046 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda ? v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb = (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error(e d ). (4) integral non-linearity(e l(adj) ). (5) center of a step of the actual transfer curve. fig 4. adc conversion characteristics
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 24 of 37 10. dynamic characteristics table 6. dynamic characteristics t amb = 0 c to 70 c for commercial applications, -40 c to +85 c for industrial applications, v ddc , v dd(io) over ranges [1] symbol parameter conditions min typ [1] [2] max unit external clock f osc oscillator frequency 10 - 25 mhz t cy(clk) clock cycle time 40 - 100 ns t chcx clock high time t cy(clk) 0.4 - - ns t clcx clock low time t cy(clk) 0.4 - - ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns port pins (except pio2 and pio3) t r(o) output rise time - 10 - ns t f(o) output fall time - 10 - ns i 2 c-bus pins (pio2 and pio3) t f(o) output fall time v ih to v il [1] [2] [3] 20 + 0.1 c b - - ns [1] parameters are valid over operating temperature range unless otherwise specified. [2] typical ratings are not guaranteed. the values listed are at room temperature (25 c), nominal supply voltages. [3] bus capacitance c b in pf, from 10 pf to 400 pf. 11. application information 11.1 xtal1 input the input voltage to the on-chip oscillators is limited to 1.8 v. when the oscillator is driven by a clock in slave mode, it is re commended that the input is coupled through a capacitor with c i = 100 pf. to limit the input voltage to the specified range, an additional capacitor connected to ground (c g ), attenuates the input voltage by a factor c i / (c i + c g ). in slave mode, a minimum input voltage of 200 mv (rms) is needed. 11.1.1 xtal and rtc printed circuit board (pcb) layout guidelines the crystal should be connected on the pcb as close as possible to the device?s oscillator input and output pins. the load capa citors cx1 and cx2 and cx3, in case of third overtone crystal usage, must have a common ground plane. in addition, the external components must also be connected to the ground plain. any loops must be made as small as possible to keep the noise coupled and parasitics in via the pcb as small as possible. the values of cx1 and cx2 should be chosen smaller accordingly to the increase in parasitics of the pcb layout. the MPT612 ic can be used with accompanying software only. the MPT612 software stack is designed to cater to different ty pes of applications in the solar pv domain ranging from simple mppt charge controlle r to advanced systems on street lighting applications to micro-inverters and dc-dc converters per panel.
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 25 of 37 12. MPT612 software overview the MPT612 ic can only be used with ac companying software. the MPT612 software stack is designed to meet the needs of di fferent solar pv domain applications ranging from mppt charge controllers to advanc ed street lighting system applications. ? scalable software modules. only those modules that are developed and tested are included in the final application image ? implementation of the mppt algorithm (patent pending) for generating maximum power from photovoltaic panel ? easy to implement apis for use with a range of peripherals ensure fast application programming ? easy configuration for use with any pv panel ? easy configuration for use with any battery (up to 4 stage charging cycle) ? available for different ide tools ? up to 15 kb of flash memory available for application software ? data logging capability through external memory ? complies with industry standard misra guidelines ? context-based api reference manual (included in the MPT612 user manual) ? distributed as libraries (object f iles) can be linked to application
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 26 of 37 12.1 architecture brb513 sample charge controller and load-control application saftey check status indication buck boost change data log lead-acid battery charging module charge cycle implement batt config batt data log mpptcore hardware functional abstraction layer (hfal) MPT612 ic system hardware sample application 2 sample application 1 MPT612 ic + sw mpp tracking module mppt cor config mppt saftey check fig 5. MPT612sw architecture 12.2 MPT612 software modules this module consists of two sub modules: hardware functional abstraction layer (hfal) and mpptcore. both these sub modules are delivered as software libraries together with the MPT612 ic. it is mandatory to use these modules to access the MPT612?s mppt functionality. 12.2.1 hardware functional abstraction layer (hfal) this module contains the functional abstraction of different peripherals that are of interest to the application layer as well as different modules of MPT612 software. this layer contains mini kernel functionality such as implementations of a round-robin scheduler, task creation and software timers. these func tions are useful during development of applications based on the MPT612. a range of different peripherals used in t he application, such as pwm, interrupts, software timers, gpio, uart and flash can be accessed using this module. in addition, utilities for logging the data onto the flash and printing the messages onto the console screen are accessed from this layer.
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 27 of 37 12.2.2 mpptcore module this module contains the maximum powerpoint tracking (mppt) algorithm. this algorithm continuously tracks the maximum power point of the pv panel and makes the system to operate at the mpp which ensure s the maximum power is generated from the pv. this module supports the well documented apis that aid in application programming. typical module functionality includes, starting the mpp tracking algorithm, enabling/disabling the mpp tracking algorithm and retrieving logged parameters from the mpptcore module. 12.3 lead-acid battery charging module this is an optional software library provided along with the MPT612 ic. this module implements the lead-acid battery charge cy cle for 2-stage, 3-stage and 4-stage batteries. using the easy configuration for the battery parameters and well documented apis, the user can design an application with ease. this module together with the MPT612sw will help in the creation of power management systems for battery charging for home and street lighting applications. 12.4 sample charge controller and load control application this module implements the sample charge controller and load control application for the specification of the MPT612 reference b oard. it uses features of the MPT612sw and lead-acid battery charging module to implement a typical charge cont roller application. 12.5 sample applications using MPT612sw and lead-acid battery charging module, solutions for several applications can be generated such as: ? dusk-to-dawn lighting applications ? street lighting applications ? traffic lighting applications ? solar based mobile chargers ? dc-dc converters in panels ? micro inverters. in the sw architecture diagram shown in fig 5 , sampleapplication1 w ill interact directly with mpptcore module to extract the maximu m power which can use a micro-inverter, to feed it to the grid. sampleapplication2 utiliz es the services of the battery charging algorithm to charge the battery and can be us ed to control different lighting applications.
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 28 of 37 13. MPT612sw interfaces 13.1 hardware functional ab straction layer interfaces table 7. hfal interfaces interface description nxlibmpt_hfal_irq_installhandler installs th e interrupt handler for the irq mentioned nxlibmpt_hfal_irq_freehandler frees the interrupt handl er installed using nxlibmpt_hfal_irq_installhandler nxlibmpt_hfal_irq_enable enables the interrupt associated with an irq nxlibmpt_hfal_irq_disable disables the interrupt associated with an irq nxlibmpt_hfal_irq_setpriority sets the priori ty of the interrupt associated with an irq nxlibmpt_hfal_irq_getpriority r eads the priority of the interrupt associated with an irq nxlibmpt_hfal_irq_saveflags saves the current in terrupt enable state and disables the interrupts nxlibmpt_hfal_irq_restoreflags restores the previous interrupt state (enable/disable) nxlibmpt_hfal_schedular_restoreflags restores t he previous scheduler state (enable/disable) nxlibmpt_hfal_schedular_saveflags saves the current scheduler state and then disables the scheduler nxlibmpt_hfal_task_create creates a task wi th given round-robin time slice in ticks nxlibmpt_hfal_timer_create creates a soft ware timer and returns the timer id nxlibmpt_hfal_timer_delete deletes the created software timer nxlibmpt_hfal_timer_checktimeout checks if the softwa re timer is running and triggers it, when necessary nxlibmpt_hfal_timer_start starts the software timer nxlibmpt_hfal_timer_stop stops the software timer nxlibmpt_hfal_timer_delay delays the execut ion till the specified timeout elapses nxlibmpt_hfal_timer_settimeout sets t he timeout value for the software timer nxlibmpt_hfal_timer_gettimeout reads the cu rrent timeout value of the software timer nxlibmpt_hfal_pwm_init initializes the pwm unit nxlibmpt_hfal_pwm_setdutycycle se ts the duty cycle of the pwm pin nxlibmpt_hfal_pwm_getdutycycle reads the current duty cycle of the pwm pin nxlibmpt_hfal_pwm_setcount sets the dut y cycle count of the specified pwm pin nxlibmpt_hfal_pwm_getcount reads the curren t duty cycle count of the specified pwm pin nxlibmpt_hfal_gpio_init initializes the gpio pin direction (input/output) nxlibmpt_hfal_gpio_setvalue sets the valu e of the gpio pin to the entered value nxlibmpt_hfal_gpio_getvalue reads t he current value of the gpio pin nxlibmpt_hfal_flash_erase erases the flash blocks nxlibmpt_hfal_flash_read reads the data from the specified flash address nxlibmpt_hfal_flash_write data is wri tten to the specified flash address nxlibmpt_hfal_datalog_init initializes the data logging module nxlibmpt_hfal_datalog_readdata_latest reads the recent dat a that is logged nxlibmpt_hfal_datalog_writedata writes the log data to the flash nxlibmpt_hfal_adc_readcounts reads the adc channel and returns the counts corresponding to the incoming signal nxlibmpt_hfal_uart_init initializes the c onsole uart port at the specified frequency nxlibmpt_hfal_uart_writebyte writes a byte to the uart console
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 29 of 37 interface description nxlibmpt_hfal_uart_readbyte reads a byte from the uart console nxlibmpt_hfal_uart_iskeypressed returns key down status to the uart console nxlibmpt_hfal_uart_flushfifo flushes the uart console port fifo nxlibmpt_hfal_util_puts writes a string to the uart console port nxlibmpt_hfal_util_gets reads a stri ng from the uart console port nxlibmpt_hfal_util_printnum prints a numbe r on the uart console port in decimals nxlibmpt_hfal_util_atoi converts from string to integer number nxlibmpt_hfal_util_memcpy copies the me mory contents from one buffer to another nxlibmpt_hfal_util_memset fills the memory locations with the pattern provided nxlibmpt_hfal_util_memcmp returns the comparison of two specified buffers nxlibmpt_hfal_util_iskeypressed returns key down status on the uart port nxlibmpt_hfal_util_flush flushes all t he data present in the uart port buffer nxlibmpt_hfal_led_init init ializes the led module nxlibmpt_hfal_led_blink_enable enables the blinking of the specified led nxlibmpt_hfal_led_blink_disable disables the blinking of the specified led nxlibmpt_hfal_sysparams_isparamvalid returns the status of the specified parameter consistently has a longer duration than the reference provided 13.2 mpptcore module interfaces table 8. mpptcore interfaces interface description nxlibmpt_mpptcore_init initializ es the mpptcore module with the pv panel configuration parameters nxlibmpt_mpptcore_setparams sets the r equired parameters in mpptcore module nxlibmpt_mpptcore_getparams reads the current mpptcore module parameters nxlibmpt_mpptcore_getlogparam s reads the logged parameters from mpptcore module nxlibmpt_mpptcore_start starts the mpp tracking algorithm nxlibmpt_mpptcore_enable enables the previously disabled mpp tracking algorithm nxlibmpt_mpptcore_disable disables the mpp tracking algorithm nxlibmpt_mpptcore_isenabled return s the status of mpp tracking al gorithm (enabled or disabled) nxlibmpt_mpptcore_get status reads the current stat us of the mpptcore module
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 30 of 37 13.3 lead-acid battery charging module interfaces table 9. mpptcore interfaces interface description nxlibmpt_batla_init initializes the lead-acid battery charging module with the battery configuration parameters nxlibmpt_batla_setparams sets the parameters required in lead-acid battery charging module nxlibmpt_batla_getparams reads t he current parameters stored in lead-acid battery charging module nxlibmpt_batla_getlogpar ams reads the logged parameters in lead-acid battery charging module nxlibmpt_batla_start st arts the lead-acid battery charging algorithm nxlibmpt_batla_enable enables the lead-acid battery charging algorithm nxlibmpt_batla_disable disables the lead-acid battery charging algorithm nxlibmpt_batla_isenabled returns the status of lead-acid battery charging algorithm enabled or disabled nxlibmpt_batla_get status reads the status of the lead-acid battery charging module 13.4 interfaces to be implemented by application table 10. mpptcore interfaces interface description nxlibmpt_hfal_sysparams_init called during system initialization. typically this api should be implemented to store any init ialized system parameters data nxlibmpt_hfal_sysparams_readpvparams retu rns the pv voltage an d current values nxlibmpt_hfal_sysparams_readbatvoltage returns the lead-acid battery voltage nxlibmpt_hfal_sysparams_readbatcurrent returns the lead-acid battery current nxlibmpt_hfal_sysparams_readloadcu rrent returns the load current nxlibmpt_hfal_sysparams_readbattemperat ure returns the battery temperature nxlibmpt_hfal_sysparams_getpvopenckt_vol tage returns the pv open circuit voltage nxlibmpt_hfal_sysparams_bringpvvg_tonewlevel se ts the pv voltage to a new voltage specified nxlibmpt_hfal_sysparams_switchled_on switches on the specified led nxlibmpt_hfal_sysparams_switchled_o ff switches off the specified led
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 31 of 37 14. package outline unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z y w v references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 7.1 6.9 0.5 9.15 8.85 0.95 0.55 7 0 o o 0.12 0.1 0.2 1 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot313-2 ms-026 136e05 00-01-19 03-02-25 d (1) (1) (1) 7.1 6.9 h d 9.15 8.85 e z 0.95 0.55 d b p e e b 12 d h b p e h v m b d z d a z e e v m a 1 48 37 36 25 24 13 a 1 a l p detail x l (a ) 3 a 2 x y c w m w m 0 2.5 5 mm scale pin 1 index lqfp48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm sot313-2 fig 6. package outline
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 32 of 37 15. abbreviations table 11. abbreviations acronym description adc analog-to-digital converter amba advanced microcontroller bus architecture apb advanced peripheral bus dcc debug communications channel dsp digital signal processor fifo first in, first out fiq fast interrupt request gpio general purpose input/output iap in-application programming irq interrupt request isp in-system programming mppt maximum power point tracking pio programmable input output pll phase-locked loop pv photovoltaic pwm pulse-width modulator spi serial peripheral interface sram static random access memory ssi synchronous serial interface ssp synchronous serial port ttl transistor-transistor logic uart universal asynchronous receiver/transmitter vic vectored interrupt controller 16. revision history table 12. revision history document id release date data sheet status change notice supersedes MPT612 v.1 20100615 objective data sheet - -
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 33 of 37 17. legal information 17.1 data sheet status document status [1] [2] product status [3] definition objective [short] data sheet development th is document contains data from the objec tive specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this docu ment contains the product specification. [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may diffe r in case of multiple devices. the latest product status information is available on the internet at url http://www.nxp.com . 17.2 definitions draft ? the document is a draft version only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request via the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values w ill permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the genera l terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semicond uctors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconductors products by customer. no offer to sell or license ? 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nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 34 of 37 nxp semiconductors accepts no liability for inclusion and/or use of non- automotive qualified products in autom otive equipment or applications. in the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product wi thout nxp semiconductors? warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product clai ms resulting from customer design and use of the product for automotive applications beyond nxp semiconductors? standard warranty and nxp semiconductors? product specifications. 17.4 trademarks notice: all referenced brands, product names, service names and trademarks are property of their respective owners. i 2 c-bus ? is a trademark of nxp b.v. 18. contact information for sales office addresses, please send an email to: salesaddresses@nxp.com for additional information, please visit: http://www.nxp.com
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 35 of 37 19. list of figures fig 1. block di agram ................................................... 3 fig 2. pin confi guration .............................................. 4 fig 3. system memory map ...................................... 10 fig 4. adc conversion c haracteristics ...................... 23 fig 5. MPT612sw arch itecture................................. 26 fig 6. package outline .............................................. 31
nxp semiconductors MPT612 maximum power point tracking ic MPT612 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2010. all rights reserved. objective data sheet rev. 01 ? 15 june 2010 36 of 37 20. list of tables table 1. ordering info rmation ......................................... 3 table 2. pin descr iption .................................................. 5 table 3. limiting values ................................................ 19 table 4. static characteristics [1] .................................... 20 table 5. adc static char acterist ics.............................. 22 table 6. dynamic charac teristics .................................. 24 table 7. hfal inte rfaces .............................................. 28 table 8. mpptcore in terfaces ..................................... 29 table 9. mpptcore in terfaces ..................................... 30 table 10. mpptcore in terfaces ..................................... 30 table 11. abbrevia tions .................................................. 32 table 12. revision hi story............................................... 32
nxp semiconductors MPT612 maximum power point tracking ic please be aware that important notices concerning this document and the product(s) described herein, have been included in the section 'legal information'. ? nxp b.v. 2010. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com date of release: 15 june 2010 document identifier: MPT612 21. contents 1. general description............................................. 1 2. features and benefits ......................................... 2 3. applications......................................................... 2 4. ordering information .......................................... 3 5. block di agram...................................................... 3 6. pinning information ............................................ 4 6.1 pinning ............................................................... 4 6.2 pin descr iption.................................................... 5 7. functional description ........................................ 9 7.1 architectura l overview ........................................ 9 7.2 on-chip flash pr ogram me mory.......................... 9 7.3 on-chip stat ic ram ............................................ 9 7.4 memory map .................................................... 10 7.5 interrupt c ontrolle r ............................................ 10 7.5.1 interrupt sources .............................................. 11 7.6 pin connec t block ............................................. 11 7.7 fast general pur pose paral lel i/o ..................... 11 7.8 10-bit adc........................................................ 12 7.9 uarts.............................................................. 12 7.10 i 2 c-bus serial i/ o contro llers ............................ 12 7.11 spi serial i/o contro ller .................................... 13 7.12 ssp serial i/o contro ller ................................... 13 7.13 general purpose 32-bit timers/external event counter s ........................................................... 13 7.14 general purpose 16-bit timers/external event counter s ........................................................... 14 7.15 watchdog ti mer ................................................ 15 7.16 real-time clock................................................. 15 7.17 system control ................................................. 15 7.17.1 crystal o scillat or............................................... 15 7.17.2 pll................................................................... 15 7.17.3 reset and wake -up ti mer ................................. 16 7.17.3.1 wake-up timer descrip tion................................ 16 7.17.4 code security (cod e read pr otection)............. 17 7.17.5 external inte rrupt i nputs ................................... 17 7.17.6 memory mappi ng cont rol.................................. 17 7.17.7 power control ................................................... 17 7.17.8 apb.................................................................. 18 7.17.9 emulation a nd debug ging ................................ 18 7.17.10 embedde dice.................................................. 18 7.17.11 realmoni tor...................................................... 19 8. limiting values .................................................. 19 9. static charac teristics ........................................ 20 10. dynamic char acteris tics ................................... 24 11. application information .................................... 24 11.1 xtal1 in put...................................................... 24 11.1.1 xtal and rtc printed circuit board (pcb) layout gui delines............................................... 24 12. MPT612 software overview ............................... 25 12.1 architec ture ...................................................... 26 12.2 MPT612 software modules............................... 26 12.2.1 hardware functional abstraction layer (hfal) ......................................................................... 26 12.2.2 mpptcore module........................................... 27 12.3 lead-acid battery charging module.................. 27 12.4 sample charge controller and load control applicat ion ........................................................ 27 12.5 sample app licati ons ......................................... 27 13. MPT612sw in terfa ces ....................................... 28 13.1 hardware functional abstraction layer interf aces.......................................................... 28 13.2 mpptcore modul e interf aces .......................... 29 13.3 lead-acid battery charging module interfaces ......................................................................... 30 13.4 interfaces to be implemented by application .... 30 14. package outline ................................................. 31 15. abbreviations..................................................... 32 16. revision history................................................. 32 17. legal information .............................................. 33 17.1 data shee t status ............................................. 33 17.2 defini tions......................................................... 33 17.3 disclai mers....................................................... 33 17.4 trademar ks ...................................................... 34 18. contact information .......................................... 34 19. list of figures..................................................... 35 20. list of tables ...................................................... 36 21. contents ............................................................. 37

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